The present invention relates to a semiconductor memory device, and more particularly to a multilevel non-volatile semiconductor memory device exhibiting a stable reading operation.
The multilevel non-volatile semiconductor memory device has memory cells, each of which allows reading out operation of informations of two or more bits. FIG. 1 is a block diagram illustrative of a conventional multilevel non-volatile semiconductor memory device which controls a constant reading out time period and a word level. The information storage unit comprises a memory cell array 901 which is capable of setting plural threshold values. Namely, the conventional multilevel non-volatile semiconductor memory device has the memory cell array 901, a word level generator circuit 902 generating a word level which corresponds to a threshold value, and a sense amplifier 903 reading out an information. The memory cell array 901 is connected to the word level generator circuit 902. The memory cell array 901 is connected to the sense amplifier 903.
A delay circuit 904 is also provided which is connected to the word level generator circuit 902 and also connected to the sense amplifier 903. The delay circuit 904 controls a constant reading out time period and a word level generation time period. A read-out signal 905 is inputted into the delay circuit 904, whereby the delay circuit 904 generates a read-out start pulse signal which is transmitted to the sense amplifier 903, so that the sense amplifier 903 starts the read-out operation. FIG. 2 is a diagram illustrative of the word level, the sense amplifier operation and the read-out start signal of the conventional multilevel non-volatile semiconductor memory device of FIG. 1. The word level generator circuit 902 sequentially generates different word levels 1, 2 and 3. Namely, the first word level 1 is generated in a first read out time period 1, during which the sense amplifier 903 reads out informations from memory cells in the memory cell array 901, wherein the memory cells turned on by the first word level VT0. The second word level 2 is generated in a second read out time period 2, during which the sense amplifier 903 reads out informations from memory cells in the memory cell array 901, wherein the memory cells turned on by the second word level VT1. The third word level 3 is generated in a third read out time period 3, during which the sense amplifier 903 reads out informations from memory cells in the memory cell array 901, wherein the memory cells turned on by the third word level VT2.
Meanwhile, the multilevel non-volatile semiconductor memory device may have dummy memory cells in addition to the memory cells.
In Japanese laid-open patent publication No. 6-60678, it is disclosed that dummy cells have a higher threshold voltage than selecting word levels effective to select the memory cells, and a dummy cell selecting circuit is also provided for selecting the dummy cells in synchronous with the selecting operation to memory cell array. Further a first stage amplifier circuit is provided which includes an amplifying MOSFET which has a source, into which a read out current is supplied through the dummy cell selecting circuit. A read out operation end timing signal is generated in accordance with an output from a drain of the amplifying MOSFET.
The former one of the above described conventional multilevel non-volatile semiconductor memory device has the following problems. It is difficult to avoid or control variations in threshold voltage of the plural memory cells in the memory cell array, wherein the variations are due to the manufacturing processes. The variations in threshold voltage of the plural memory cells in the memory cell array causes a first problem in difficulty for the delay circuit 904 to control the read-out time period. FIG. 3 is a variation in the necessary time for the sense amplifier to perform read-out operation as a sense amplifier ability over voltage, wherein a read line represents the sense amplifier whilst a broken line represents the delay circuit. As the voltage is low, the necessary time for the sense amplifier to perform read-out operation is long and the sense amplifier ability is low. As the voltage is high, the necessary time for the sense amplifier to perform read-out operation is short and the sense amplifier ability is high. However, the voltage is further increased, then a rate of shortening the necessary time for the sense amplifier to perform read-out operation becomes low. The constant read-out time period is controlled by the delay circuit 904. It is possible that the constant read-out time period is shortened to be insufficient when a power voltage is changed to high or low voltage levels from the necessary level for the sense amplifier, whereby the read-out time period is ended without turning the selected memory cells ON.
If the read-out time period is intentionally extended to avoid the above problem, then another problem is raised, wherein the read-out time period is restricted in accordance with a regulation. Namely, it is necessary that the read-out time period is set to be sufficiently short for complying with the regulation. The read-out time period depends upon an ambient temperature.
The extension of the read-out time period also raises another problem in that the memory cells erroneously turn ON even the memory cells should have to turn OFF. FIG. 4 is a diagram illustrative of variations in word level over time when the word level is supplied to the memory cell, when there is a difference in threshold voltage between an upper limit of memory cells which should turn ON and a lower limit of other memory cells which should turn OFF and also when the word level is high as a word level xe2x80x9cAxe2x80x9d. In this case, if the read-out time period is extended, then all of the memory cells which should turn ON are turn ON, whilst some of the other memory cells which should turn OFF are erroneously turn ON. If the read-out time period is extended beyond the acceptable time period, then a slight increase in the word level causes the other memory cells, which should turn OFF, to turn ON.
The word level generator circuit 902 generates a word level which is slightly higher than the threshold level of the memory cells which should turn ON based on the threshold level. As described above, it is difficult to precisely control the threshold level of the memory cells, for which reason it is difficult to precisely control the word level. If the word level is as a word level xe2x80x9cBxe2x80x9d which is slightly higher than the upper limit of the memory cells which should turn ON, then it is necessary that the read out time period is set long until entering into an OK2 region. If the word level is as the word level xe2x80x9cAxe2x80x9d which is extensively higher than the upper limit of the memory cells which should turn ON, then the extension of the read out time period to enter into an NG1 region causes the memory cells which should turn OFF to erroneously turn ON.
As described above, it is important for the read out operation from the memory cells to take a matching between the read out time period and the word level. Notwithstanding, it is difficult for the conventional circuit configuration to control the threshold voltage of the memory cells and also to control both the read out time period and the word level.
The above Japanese publication No. 6-60678 is silent on detection and control to the word level in the multilevel memory system.
In the above circumstances, it had been required to develop a novel multilevel non-volatile semiconductor memory device free from the above problems.
Accordingly, it is an object of the present invention to provide a novel multilevel non-volatile semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel multilevel non-volatile semiconductor memory device which is capable of controlling an optimum read-out time period for the sense amplifier ability under given power voltage and ambient temperature.
It is still further object of the present invention to provide a novel multilevel non-volatile semiconductor memory device which is capable of realizing a highly accurate control to the word level.
It is yet a further object of the present invention to provide a novel multilevel non-volatile semiconductor memory device which exhibits highly stable read out operations.
The present invention provides a multilevel non-volatile semiconductor memory device comprising: plural memory cells having plural threshold levels for allowing the plural memory cells to turn ON or OFF in accordance with relationships of word levels to the plural threshold levels; a word level generator circuit generating the word levels in every read out time periods for the plural threshold levels; a memory cell read-out circuit for reading out informations from the memory cells; dummy memory cells receiving inputs of the word levels and having substantially the same threshold levels as the memory cells for allowing the dummy cells to turn ON with delay from the memory cells; and a read out end timing controller for controlling the word level generator circuit to discontinue rising the word level when the dummy memory cell turns ON, and also for controlling the memory cell read-out circuit to finish the read out operations.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.